Physical Design Lead Engineer

Cisco Systems, Inc.
United States, California, San Jose
170 W Tasman Dr (Show on map)
May 23, 2025
Application Window Expected to close 06/30/25. Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed. Your Impact As a Technical Leader, you will be responsible for overseeing the design and verification of application-specific integrated circuits (ASICs), ensuring they meet performance, power, and area specifications. This role involves coordinating cross-functional teams, guiding design methodologies, and addressing technical challenges throughout the development process to ensure successful tape-out and compliance with industry standards. Responsibilities include: Lead chip-level PNR activities, from floor planning, bump and rdl planning, power grid design to clock planning, routing, and timing closure. Perform full chip DRC/LVS/ERC/ANT checks, review and debug the issues, provide solutions and ensure signoff clean results. Work closely with block and TOP level physical implementation, IP development teams and to resolve PV issues and address to proper owners. Deploy and improve physical verification flows and methodologies. Develop custom check as per need for verification robustness. Guide and mentor a team of physical design engineers on project-level backend implementation and partner closely with frontend, integration, and verification teams. Minimum Qualifications: BS/MS in Electrical Engineering or Computer Science, with 10+ year minimum of hands-on experience in ASIC implementation and Physical verification Experience in deep submicron CMOS technologies. Experience with physical verification (DRC, LVS, ERC, ANT), debug, and solution. Scripting experience in TCL, Perl, or Makefile to streamline and automate workflows. Experience working with one or more of the following physical design tools, such as Cadence, Innovus, Synopsys IC Compiler, or Fusion Compiler. Preferred Qualifications: Extensive experience working with block or full chip physical verification and/or owning Physical Verification CAD flow development and support. Experience on 5nm nodes and below. Experience working with semiconductor foundries on installation and maintenance of process design kits (PDKs) for SOC physical design teams. Experience working with Package and floorplan teams to define padring and bump-map design. Why Cisco? At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Simply put - we power the future. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.