Senior Staff Engineer, RD Verification

Responsible for design verification of integrated circuits, using both directed tests and constrained random regressions. Focuses on digital design verification, but proficiency with mixed signal design verification and creation/validation of models are strong advantages. Proficiency in System Verilog and UVM, including: writing checkers and assertions, customizing constraints, and getting functional coverage collection using cover groups. Technical leadership both within the internal project DV team, but also directly supporting demanding customers. Creating test benches and automated verification simulations. Performs block level and top-level design verification. Generates relevant documentation (DV Plan, DV execution plan, and customer reviews). Hybrid work policy w/in commuting distance.

• Master's degree in Electronics, Electrical Engineering, VLSI, or a related field
• 7 years of experience in design verification of integrated circuits, using both directed and constrained random regressions; utilizing System Verilog and UVM (including writing checkers and assertions); customizing constraints; using cover groups for functional coverage collection; creating testbenches and automated verification stimulus; and generating relevant documentation
• 5 years to include: design verification of system architecture
• 4 years to include: design verification of sensor technologies
• 3 years to include: direct collaboration with stakeholders; and conducting mixed signal verification, creation, and validation of models
• 1 year to include: Intellectual Property Verification