New 
Senior Silicon Logic Design Engineer
 Microsoft | |
 United States, North Carolina, Raleigh | |
 Jul 13, 2025 | |
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OverviewMicrosoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Cloud Compute Development Organization (CCDO) Logic Design team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Senior Silicon Logic Design Engineer to join the team.
ResponsibilitiesIn this role, you will be an integral part of the Logic Design Team, contributing to micro-architecture implementation, RTL coding, IP and subsystem development, and SoC integration, along with design quality assurance. Your responsibilities include:Implementing micro-architectural specifications in Verilog or SystemVerilogExpanding your micro-architectural knowledge and contributing to unit, subsystem, and SoC-level architectureDeveloping and integrating various functional block RTLs into SoC RTLPerforming design quality checks such as timing closure, lint, CDC, synthesis, and low power intentCollaborating with the verification team to ensure functional correctnessInterfacing with performance modeling, physical design, design-for-test, and other teams to deliver qualified physical partitionsWriting basic tests and debugging features at IP and SoC levels as neededAutomating tasks using scripting to improve efficiencyDelivering high-quality functional blocks on schedule with professional integrityChallenging the status quo with a growth mindsetMentoring junior team members and summer interns as part of a growing team | |