RTL/Logic Design Engineer

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THE ROLE:

The Graphics Memory Controller (GMC) is an IP that delivers into AMD's Discrete GPU (Navi) and Instinct (HBM) based SOCs that are shipped by AMD's Radeon Technology Group. We deliver discrete graphics, Data Center GPUs and Game Console APUs using a flexible controller design as the base for all our IP. We are looking for an experienced, conscientious logic design engineer in the Dram Controller IP at AMD's Santa Clara Design Center. You will be working in a fast-paced, complex environment where you will be challenged to provide elegant, robust solutions for increasingly complex features.

THE PERSON:

The ideal candidate for this role is an experienced and detail-oriented logic design engineer with a strong background in RTL development and a commitment to advancing graphics technologies. With over five years of experience in digital design, they bring expertise in high-speed memory interfaces such as HBM and GDDR and have a proven ability to deliver high-performance designs that meet timing, power, and area requirements. They are proficient in Verilog and familiar with industry-standard CAD tools from Synopsys, Cadence, and Mentor Graphics, with strong skills in simulation, synthesis, and timing analysis. This individual works effectively in dynamic, collaborative environments, communicates clearly across teams, and demonstrates strong analytical and problem-solving abilities. Their initiative and attention to detail make them a valuable contributor to AMD's Santa Clara Design Center, where they will support the development of next-generation discrete GPUs and data center solutions.

KEY RESPONSIBILITIES:

• Participate in the development of Architecture and Micro-architecture specifications for the Logic components.
• Perform logic design, Register Transfer Level (RTL) coding for new features within existing blocks and design new blocks supporting HBM and GDDR DRAM Technologies
• Deliver Designs that meet functional and performance requirements,
• Deliver Design that meets physical/structural design constraints (timing, area, power)
• Work with Verification Engineers to effectively communicate and resolve issues from test plan through feature bring up to coverage closure

PREFERRED EXPERIENCE:

• Logic design implementation using hardware description language (RTL)
• Experience working on DRAM or similar high-speed interfaces is a big plus
• Usage/execution of logic simulation, synthesis and familiarity with logic development flows
• Strong RTL analysis skills including Verilog, Timing Analysis
• Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics
• Strong communication, Time Management, and Presentation Skills
• Must be a self-starter, and be able to independently and efficiently drive tasks to completion
• Excellent analytical and problem-solving skills along with attention to details
• Aware of latest Power -aware design methodologies

ACADEMIC CREDENTIALS:

• Bachelor's or master's degree in computer engineering, Electrical Engineering, or a related field.

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