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Senior Quality Engineer (Automation)

UST
United States, Colorado, Denver
Jan 10, 2026
Role description

Key Responsibilities:



  • Develop and implement constrained-random verification environments using
    SystemVerilog and UVM.
  • Write and execute test plans, testcases, scoreboards, monitors, and coverage
    models.
  • Debug and analyze test failures to identify RTL or testbench issues.
  • Collaborate closely with RTL designers, architecture, and firmware teams to ensure
    design correctness and coverage closure.
  • Develop reusable verification components and contribute to the improvement of the
    verification infrastructure and methodology.
  • Analyze functional and code coverage metrics; drive coverage closure.
  • Participate in design and verification reviews and provide feedback on specifications
    and testability.
    Required Qualifications:
  • Bachelor s or Master s degree in Electrical Engineering, Computer Engineering, or
    related field.
  • 4+ years of experience in ASIC/SoC verification using SystemVerilog and UVM.
  • Strong understanding of digital design and verification fundamentals.
  • Experience with simulation tools (e.g., VCS, Questa, Incisive) and waveform viewers
    (DVE, Verdi).
  • Proficiency in scripting languages (e.g., Python, Perl, Shell, TCL) for automation.
  • Strong debugging and problem-solving skills.
  • Experience with version control systems (Git, Perforce) and bug tracking tools.

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