Sr. Design Verification Engineer, AI Hardware

The Tesla AI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Dojo is Tesla's custom supercomputer built for massive scale inference. Powered by the next generation architecture, Dojo enables real time AI workloads for Full Self Driving (FSD) and Optimus, while unlocking new frontiers in video generation and space based data center deployment. Training remains a core capability, but Dojo's primary mission is delivering high throughput, low latency inference at a scale never seen before. Tesla's AI Hardware team is building the silicon that will define the next era of AI - on Earth and beyond.

Tesla is looking for Senior, Staff level Design Verification Engineer for Pre-Silicon Verification of block and top-level SoC for next-generation Dojo AI accelerator. You will work with cross-functional teams to build a metric-driven, configurable, and flexible verification environment, while also contributing to architecture, post-silicon validation, and SoC bring-up to solve real-world system scenarios. You will work with a team ofhighly talentedengineers who are focused on advancing Tesla's AI mission. If you love solving challenging problems, you will fit in very well with our culture.

This role is open in both Palo Alto, CA and Austin, TX.

• Plan the verification of complex digital design blocks by understanding design specifications and collaborating with Design, Architecture, SW, FW, and external IP delivery teams to identify critical verification scenarios for Dojo AI accelerator
• Architect and deploy exhaustive highly reusable UVM testbenches, writing complex sequences, scoreboards and SVA to verify custom AI hardware blocks like compute-cores, NoC, DMA engines
• Design and own the verification of portable reusable testbenches around boot-subsystems, vendor-IP-subsystems and SoC top
• Collaborate closely with RTL Design, Architecture, Firmware, and System/SW Engineers to define verification strategies and root-cause RTL bugs
• Create coverage driven verification plans from specifications; define and implement comprehensive coverage models to measure stimulus quality and track progress towards tapeout
• Design C, C++ and Python based stimulus to drive SoC verification efforts

• Degree in Electrical Engineering, Computer Engineering, or Computer Science or equivalent experience
• 5+ years of experience in block, vendor-IP and SoC verification, with deep expertise in SystemVerilog and UVM
• Experience verifying Compute-cores, NoC, DMA engines, memory and IO subsystems at block and SoC levels
• Emulation experience on platforms such as Palladium or Zebu
• Proven track record in SoC bring-up and post-silicon validation
• Excellent programming skills in C/C++, Python/Perl, and Assembly for embedded systems or modeling
• Experience using AI toolchain for faster development in various stages of verification including test-planning, TB-development, debug and coverage closure
• Strong communication skills to work independently in a fast-paced, agile, cross-functional team