Principal Engineer - Design Implementation

As part of the MCU IC Design-HP group, the successful candidate will be responsible for Design Implementation (Synthesis/STA/Timing closure) of 32-bit controllers. The role will include driving and optimizing synthesis, power optimization, static timing analysis, and logic verification using an industry leading ASIC design flow. It will require a proactive candidate with a proven record of success in cross functional and cross site team environments. The candidate is required to drive and enhance Synthesis, Static Timing and Power Optimization methodologies, for the MCU32 silicon design group.

Duties and responsibilities include:

• Develop timing constraints, drive SoC timing budgets, power optimization, formal verification, timing closure and other sign-off activities.
• Drive low power implementation and optimization methodologies using UPF/CPF
• Work closely with digital, analog, and physical design teams to optimize for performance, power, and area.

Requirements/Qualifications:

• Bachelor's degree in electrical engineering with at least 10+ years of experience in ASIC implementation activities such as synthesis and STA.
• Extensive experience in RTL2Netlist implementation flows
• Strong knowledge in Cadence & Synopsys tools for synthesis, static timing analysis and other activities
• Strong scripting skills in TCL, Perl and other programming languages
• Synthesis and timing closure ownership for 32-bit Microcontroller designs.
• Very good inter personal skills and able to interact well with other members in the functional teams of the business unit.
• Good communication skills.